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E2C0030-27-Y2
Semiconductor MSC7170-XX
Semiconductor
This version:MSC7170-XX Nov. 1997 Previous version: Jul. 1996
57 Dot Character 16-Digit 2-Line Display Controller/Driver with Keyscan Function
GENERAL DESCRIPTION
The MSC7170 is a display controller/segment driver containing a 5 6 keyscan circuit, designed for a 5 7 dot matrix type vacuum fluorescent (VF) display tube. Use of the MSC1164/1165 grid driver allows a maximum of 16-digit pair to be displayed, or use of the MSC7171 grid driver allows a maximum of 12 digit pairs to be displayed.
FEATURES
* Able to display 5 7 dot matrix type characters of a maximum of 16 digits 2 lines (when MSC1164/1165 is used) * The number of display digits selectable in a range of 1 digit 2 lines to 16 digits 2 lines * Standby function Combination of the MSC7171 grid driver and the MSC7170 decreases grid driver current during the standby mode of the driver. * Display intensity selectable by 10-bit digital dimming * Display characters selectable from among 256 types by internal PLA User programmable, mask option * 8-bit synchronous serial data transfer SPI interface * 5 6 keyscan circuit * Driver output current (IOH) : 1 mA (SEG1 to SEG35) : -15 mA (SEG36) * Supply voltage: VDD = 5 V10% : VDISP = 60 V (max.) * Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC7170-XXGS-BK) xx indicates the code number.
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Semiconductor
MSC7170-XX
BLOCK DIAGRAM
ROW
12345
COL
123456 ROW 1 CURSOR DATA BUFFER 16b ROW 1 DISPLAY 8 DATA BUFFER 16w8b
KBINT VDD RESET
56KEYBOARD SCANNER
VDISP SEG1-1 SEG1-2
LATCH 36 SEG DRIVER
8
LATCH 8 CHARACTER GENERATOR 256w35b
SEG1-36
35
ENABLE SIMO SCLK SOMI
SHIFT REGISTER 8
ROW 2 DISPLAY 8 DATA BUFFER 16w8b ROW 2 CURSOR DATA BUFFER 16b 8 5
LATCH
35 36
SEG2-1 SEG2-2
SEG DRIVER
LATCH
LATCH 8 COMMAND DECODER CONTROLLER
SEG2-36 VSS1
8 5
ADDRESS SELECTOR 5 4 WRITE ADDRESS COUNTER DIGIT COUNT REGISTER DUTY CYCLE COUNTER READ ADDRESS COUNTER GRID DRIVER INTERFACE
4 TIMING GENERATOR
4
ADDRESS COMPARE
4
4
STANDBY DATA CLOCK
8
VSS2 OSCI
OSC
BLANK DUTY AND BLANK GENERATOR
OSCO SYNC
AC FILAMENT SYNC
DUTY
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
VDISP SEG 2-21 SEG 2-22 SEG 2-23 SEG 2-24 SEG 2-25 SEG 2-26 SEG 2-27 SEG 2-28 SEG 2-29 SEG 2-30 SEG 2-31 SEG 2-32 SEG 2-33 SEG 2-34 SEG 2-35 SEG 2-20 SEG 2-19 SEG 2-18 SEG 2-17 SEG 2-16 SEG 2-15 SEG 2-14 SEG 2-13 SEG 2-12 SEG 2-11 SEG 2-10 SEG 2-9 SEG 2-8 SEG 2-7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
,
MSC7170-XX
VDD ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 COL4 COL5 COL6 KBINT ENABLE SIMO SCLK SOMI RESET OSCI
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
OSCO
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SYNC DATA CLOCK DUTY STANDBY VSS2 SEG 1-21 SEG 1-36 SEG 1-22 SEG 1-23 SEG 1-24 SEG 1-25 SEG 1-26 SEG 1-27 SEG 1-28 SEG 1-29 SEG 1-30 SEG 1-31 SEG 1-32 SEG 1-33 SEG 1-34 SEG 1-35 SEG 1-20 SEG 1-19 SEG 1-18 SEG 1-17 SEG 1-16 SEG 1-15 SEG 1-14 SEG 1-13
SEG 2-6 SEG 2-5 SEG 2-4 SEG 2-3 SEG 2-2 SEG 2-1 SEG 2-36 SEG 1-1 SEG 1-2 VSS1 SEG 1-3 SEG 1-4 SEG 1-5 SEG 1-6 SEG 1-7 SEG 1-8 SEG 1-9 SEG 1-10 SEG 1-11
100-Pin Plastic QFP
Note:
SEGn-x sequence depends on ROM code content and may be altered by changing segment number x relationship to ROM bit number. See Correspondence between Segment Output and VF Display Tube Dots. 3/26
SEG 1-12
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Semiconductor
MSC7170-XX
PIN DESCRIPTIONS
Pin 1 2-36 37 38-39 40 41-72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Symbol VDISP SEG2-1 to SEG2-35 SEG2-36 SEG1-1 SEG1-2 VSS1 SEG1-3 to SEG1-35 SEG1-36 SEG1-21 VSS2 STANDBY DUTY CLOCK DATA SYNC OSCO OSCI RESET SOMI SCLK SIMO Chip select input pin. Interface to the microprocessor is possible only when a logic low level is applied to this pin. The SOMI output pin is tri-stated when ENABLE is at a logic high level so that multiple devices may use the SPI network. Interrupt request output to the microprocessor for keyscan data read out. Keyscanning is started when any key is depressed or released. After completion of one cycle, KBINT goes to a logic low level to indicate new keyscan data is available. KBINT remains low until execution of Keyscan Data Output command. Column 1-6 input pins from key switch matrix. A pull-up resistor is built in so that the pin is in the logic high state except when a key is depressed and a logic low level is input to the pin. High voltage power supply VF tube 57 dot anode driver outputs. These pins may be connected directly to the VF tube. VF tube cursor driver output. VF tube 57 dot anode driver outputs. These pins may be connected directly to the VF tube. High voltage ground VF tube 57 dot anode driver outputs. These pins may be connected directly to the VF tube. VF tube cursor driver output. VF tube 57 dot anode driver output. This pin may be connected directly to the VF tube. Logic supply ground. Grid driver standby output pin. A logic high level on this output forces the grid driver (MSC7171) into a low power standby mode. Duty cycle output pin. Grid driver clock output pin. Grid driver data output pin. AC filament synchronization input pin. Oscillator output pin. Oscillator input pin. Reset input pin. SPI data output pin. Keyscan data is shifted out on the falling edge of SCLK. SPI clock input pin. Data is shifted in on the SIMO pin on the rising edge of SCLK. SPI data input pin. Command data is shifted in on the rising edge of SCLK. Connects to crystal (or ceramic resonator) oscillator and capacitor. These pins have internal feedback resistors. Description
87
ENABLE
88
KBINT
89-94
COL6-1
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Semiconductor
MSC7170-XX
Pin 95-99
Symbol ROW5-1
Description Row 1-5 scanning signal output pins to key switch matrix. When any key is depressed or released, keyscanning is started and is continued until Keyscan Data Output command is executed. All Row 1-5 outputs go to logic low level when keyscanning is stopped. Logic voltage supply.
100
VDD
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MSC7170-XX
ABSOLUTE MAXIMUM RATINGS
Parameter Logic Supply Voltage Driver Supply Voltage Input Voltage Power Dissipation Package Thermal Resistance Driver Output Current Storage Temperature Symbol VDD VDISP VIN PD Rj-a -- TSTG Condition -- -- Applies to all inputs Ta25 \ SEG1-1 to SEG1-35 SEG2-1 to SEG2-35 SEG1-36, SEG2-36 -- Rating -0.3 to 6.0 *1 -0.3 to 65 *1, 2 -0.3 to VDD+0.3 *1 663 98 -2 -2 -15 -65 to 150 Unit V V V mW *3 C/W mA mA mA C
Notes: *1 Voltage that can be applied to GND *2 Stresses beyond the rating may cause permanent damage to the device. *3 Package thermal resistance between junction and atomsphere. Junction temperature Tj in the following expression must not exceed 150C: Tj = P Rj-a + Ta (P: maximum IC power consumption)
RECOMMENDED OPERATING CONDITIONS
Parameter Logic Circuit Supply Voltage Driver Supply Voltage Operating Temperature Symbol VDD VDISP Top Condition Usable only for logic power terminal Usable only for driver power terminal -- Range 4.5 to 5.5 7 to 60 -40 to 85 Unit V V C
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=-40 to 85C, VDD=4.5 to 5.5 V, VDISP=7 to 60 V) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current Symbol VIH VIL IIH1 IIH2 "L" Input Current IIL1 IIL2 VOH1 VOH2 "H" Output Voltage VOH3 VOH4 VOL1 VOL2 "L" Output Voltage VOL3 VOL4 VDD=5.5 V VIN=VDD VDD=5.5 V VIN=0.5 V IOH=-500 mA IOH=-1 mA IOH=-15 mA IOH=-200 mA IOL=500 mA IOL=100 mA IOL=3 mA IOL=200 mA All SEGs on, 16-digit display, maximum brightness, no load, fosc=4 MHz All SEGs off Low power mode All SEGs on, 16-digit display, maximum brightness, no load, fosc=4 MHz All SEGs off Condition -- -- Min. 0.7 VDD -- -1 -30 -1 -15 VDD-0.6 VDISP-3 VDISP-4 4 -- -- -- -- Max. -- 0.3 VDD 1 30 1 -160 -- -- -- -- VSS+0.6 2.5 3 0.5 Unit V V mA mA mA mA V V V V V V V V Applied Pin All inputs All inputs SIMO, SCLK, ENABLE, RESET COL1-6, SYNC SIMO, SCLK, ENABLE, RESET COL1-6, SYNC OSCO SEGn-1 to n-35, n=1, 2 SEG1-36, SEG2-36 DUTY, SOMI, KBINT DATA, CLOCK, STANDBY OSCO SEGn-1 to n-35, n=1, 2 SEG1-36, SEG2-36 ROW1-5, DUTY, SOMI, KBINT,DATA, CLOCK, STANDBY
IDD1
--
10
mA VDD-VSS
Power Supply
IDD2 IDD3
-- --
10 25
mA mA
IDISP1
--
15
mA VDISP-VSS
IDISP2
--
1
mA
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Semiconductor AC Characteristics (1/2)
MSC7170-XX
(Ta=-40 to 85C, VDD=4.5 to 5.5V, VDISP=7 to 60 V, fOSC=4 MHz, 12-digit display) Parameter ENABLE Setup Time ENABLE Hold Time SCLK Frequency SCLK Pulse Width SCLK Rise/Fall Time SIMO Setup Time SIMO Hold Time SOMI Output Enable SOMI Output Disable SCLK to SOMI Delay Byte Length Byte Delay SYNC Frequency Symbol tES tEH tCP tcw tcr/tcf tDS tDH tOE tOD tPD tBYTE tDELAY tSYNC Condition See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) See Fig. 1 (Data Transfer Timing) Enable to SOMI valid Enable to SOMI tri-state See Fig. 1 (Data Transfer Timing) MSB to LSB See Fig. 2 (Example of Data Transfer) MSB to LSB See Fig. 2 (Example of Data Transfer) Duty cycle=50%, fOSC-4 MHz 12-digit display fOSC=4 MHz See Fig. 5 (Duty Cycle Timing) CI=20pF Self-oscillation fOSC=4 MHz, See Fig. 3 (12-digit Display Cycle Timing) fOSC=4 MHz See Fig. 3 (12-digit Display Cycle Timing) tBLANK=48/fOSC fOSC=4 MHz See Fig. 5 (Duty Cycle Timing) fOSC=4 MHz See Fig. 3 (12-digit Display Cycle Timing) fOSC=4 MHz See Fig. 5 (Duty Cycle Timing) fOSC=4 MHz See Fig. 5 (Duty Cycle Timing) fOSC=4 MHz See Fig. 5 (Duty Cycle Timing) fOSC=4 MHz See Fig. 6 (Keyscan Timing) Min. Typ. Max. Unit 50 4 -- 250 -- 50 120 -- -- -- 3.5 --
*1
-- -- 0.5 -- -- -- -- -- -- -- -- -- --
-- -- 2 -- 500 -- -- 200 200 100 -- 20 250
ns ms MHz ns ns ns ns ns ns ns ms ms kHz
0.4
SEGn Pulse Width Operating Frequency DUTY Period
tSEG tOSC tGRID
-- 1.5 --
10 4 256
-- 4.5 --
ms MHz ms
Blank Interval (min.)
tBLANK
--
12
--
ms
DATA Pulse Width High
tDW tDATA tDC tPW tCLOCK tSCAN
--
256
--
ms
DATA Period
-- 3072 --
ms ms ms ms ms
DATA to CLOCK Delay CLOCK Pulse Width CLOCK Cycle Keyscan Cycle Time
-- -- -- --
5 250 256 40
-- -- -- --
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Semiconductor AC Characteristics (2/2)
MSC7170-XX
(Ta=-40 to 85C, VDD=4.5 to 5.5 V, VDISP=7 to 60 V, fOSC=4 MHz, 12-digit display) Parameter Keyscan Pulse Width Symbol tSPW tWAKE tr tf tr tf tr/tf CI Condition fOSC=4 MHz, See Fig. 6 (Keyscan Timing) Keypress to KBINT at "L" level fOSC=4 MHz Min. Typ. Max. Unit -- 8 -- -- 1.3 3.4 -- -- 20 6 -- 5 10 5 5 5 5 200 -- ms ms ms ms ns pF ms ms
Ceramic resonator -- Crystal -- 0.5 1 0.2 0.1 5 --
Wake-up Time
Slew Rate (SEGn-1 to SEGn-35) Slew Rate (SEGn-36) Slew Rate (DUTY, DATA, CLOCK) Input Capacitance
CL=20 pF, VDISP=60 V, VOL=6 V, VOH=50 V CL=20 pF, VDISP=60 V, VOL=6 V, VOH=50 V VOL=0.1 VDD, VOH=0.9 VDD, CL=10 pF all pins
*1) For the minimum value when digits other than 12 digits are displayed, refer to the following expression. fOSC tSYNC (Min)> 1024 (digit display number)
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MSC7170-XX
TIMING DIAGRAM
ENABLE
3.8V 0.8V
tES SIMO
3.8V 0.8V
tDS SCLK
3.8V 0.8V
tDH tcf tcw tCP tPD tOD tEH
tcr tcw tOE
SOMI
3.8V 0.8V
Figure 1. Data Transfer Timing
ENABLE SOMI SCLK tDELAY SIMO c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 s7 s6 s5 s4 s3 s2 s1 s0 tBYTE c7 c6 c5 c4 c3 c2 c1 c0
Figure 2. Data Transfer Example
DUTY DATA CLOCK tBLANK tGRID tDATA
Figure 3. 12-Digit (n=12) Display Cycle Timing
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Semiconductor
MSC7170-XX
tGRID DUTY tBLANK DATA CLOCK GRID1
Figure 4. GRID1 Interval Timing
(fosc) DATA tDC CLOCK tBLANK DUTY tDGL GRIDn SEGn-1 to n-35 SEGn-36
GRID12
tPW
tDGH
GRID1
tSEG
Note:
(fOSC) is internal to the MSC7170 and not visible externally. GRIDn are outputs of, and tDGL and tDGH are timig parameters of, the MSC7171 (grid driver). Figure 5. Duty Cycle Timing
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Semiconductor
MSC7170-XX
ROW1 ROW2 ROW3 ROW4 ROW5 KBINT
tSCAN tSPW
Figure 6. Keyscan Timing
Key Depressed KBINT SCAN ENABLE Key Command Key Command Active Active Key Depressed
Figure 7-1. Single Keypress/Single Read
Key Depressed KBINT SCAN ENABLE Null Command Key Command Active
Figure 7-2. Single Keypress/Multiple Read
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Semiconductor
MSC7170-XX
Key 1 Depressed Key 2 Depressed KBINT SCAN ENABLE Key Command Key Command Active
Figure 7-3. Multiple Keypress/Multiple Interrupt Figure 7. Typical Cases of Keyscan Operation
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MSC7170-XX
FUNCTIONAL DESCRIPTION
The MSC7170 (Dot Matrix VF Segment Driver) in conjunction with the MSC7171 (Dot Matrix VF Grid Driver) is capable of controlling a variety of dot matrix VF displays and keyboards. The MSC7170 is designed to drive the anodes of up to 32 dot matrix digits in two lines. Each digit is a 5 7 matrix of anodes, or dots, which requires a total of 70 segment driver outputs. There are two extra segment outputs for supplying drive to dedicated annunciators. The grid drivers of the MSC7171 are controlled by the MSC7170 through a two-line serial interface and a duty cycle control line, DUTY (see APPLICATION CIRCUIT). Additionally, the MSC7170 provides 10-bit digital dimming of all display data, a 56 keyscan function allowing control of up to 30 key pads and a low-power standby mode. The MSC7170 is controlled through a standard SPI interface. All MSC7170 internal timings are generated through an external 4 MHz (typ) ceramic oscillator. One display cycle is defined as up to 16384 periods of the 4 MHz (250 ns) reference in increments of 1024 periods, one for each pair of digits displayed. Display intensity is determined by the duty cycle of the DUTY output within one display increment divided by the total number of increments, or character pairs, displayed (see Display Duty Cycle Set and Number of Display Digit Pairs Set commands below). The maximum duty cycle is defined as 976 out of 1024 increments or 95.3 percent. The MSC7170 is capable of synchronizing the DUTY signal with an AC filament to avoid visible flicker during dimming conditions. This is required in VF tubes of greater than 100 mm, equivalent to 14 digits, in length. Synchronization is accomplished by alternately initiating display cycles coincident with rising and falling edges of the filament voltage. Upon completion of a rising/falling edge display cycle, the MSC7170 will wait for a falling/rising edge before initiating the next display cycle. The MSC7170 detects rising and falling edges of a CMOScompatible SYNC input derived directly from the filament voltage. The amount of hold time between display cycles varies between no delay as a minimum and the period of the filament voltage as maximum. The amount of delay should be consistent for all display cycles assuming that the filament frequency is well defined. The MSC7170 is controlled through a Serial Peripheral Interface (SPI) compatible communications port. The SPI is a high-speed synchronous serial I/O port that shifts a serial bit stream of eight data bits into or out of a device at a bit transfer rate programmed in a controlling device. The figure below shows a typical connection of the SPI for communications between a master (radio microprocessor) and slave (MSC7170). Three I/O pins are associated with the SPI interface -- SPI slave-in master-out (SIMO), SPI slave-out master-in (SOMI), and SPI serial clock (SCLK). Additionally, a separate input pin is used to enable the MSC7170 to communicate with the microprocessor through this interface.
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Semiconductor
MSC7170-XX
MASTER SIMO Serial Input Buffer Enable Slave In/Master Out SIMO
SLAVE
Serial Input Buffer
Shift Register MSB
SOMI LSB SCLK
Slave Out/Master In
SOMI MSB
Shift Register LSB
Serial Clock
Microprocessor
SCLK
MSC7170
SPI Master/Slave Connection The microprocessor provides the serial clock (500 kHz typ.) to all devices on the SPI network with a CLOCK POLARITY of 1 (inactive level is high). Data is transferred from the master (microprocessor) to the salve (MSC7170) over the SIMO line, while data is transferred from the slave to the master over the SOMI line. Data is clocked out of the transmitting device on the falling edge of SCLK and latched into the receiving device with the rising edge of SCLK. ALL data transmissions are made MSB (b7) first. A typical data transfer cycle between the microprocessor and the MSC7170 is initiated by first bringing the ENABLE line low. The first byte transmitted defines the command or operation to be executed. All remaining bytes received, prior to ENABLE being returned high, are treated as data bytes for that operation. Each command or operation executed requires a separate ENABLE transfer cycle. The maximum waiting period between byte transfers, measured from MSB to LSB, is 20 msec. All activity on the SCLK and SIMO pins while ENABLE is high is ignored. Additionally, the SOMI pin shall be in a tri-state condition when ENABLE is high so that other SPI devices on the network may drive the line without contention. The MSC7170 controls up to 30 key pads via a 5 controls up to 30 key pads via a 56 key scan circuit. COL1 to 6 (inputs) and ROW1 to 5 (outputs) are connected to an external switch matrix with an impedance of 500W max. The ROW1 to 5 outputs start scanning only when a depression or release of any key is detected. Upon completion of the first keyscan cycle, see Figure 6, the keyboard interrupt, KBINT, output is pulled low to indicate availability of new keyscan data. The keyscan circuit continues to scan and KBINT remains low until the keyscan data has been read using the Keyscan Data Output Command. In the event of a multiple key depression, a second interrupt will be generated following the clearing of the first interrupt. A stuck key switch will not generate multiple interrupts since only state transitions are detected by the keyscan circuitry. Keyscan data may be read without stopping the keyscan by using the Null Command. The keyscan data is transmitted to the microprocessor by rows as shown in the Output Data Bytes section. The output of keyscan data wraps around to the first byte for SPI transactions of more than six bytes. After completion of the last keyscan cycle all ROW outputs go to low level.
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Semiconductor
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Key switch data is latched internally for transfer to the microprocessor via the SPI port. The microprocessor may use KBINT as an interrupt request or for polling the MSC7170 to determine when new keyscan information is available. As an alternative for polling, the MSC7170 continuously outputs a status byte during any SPI transaction, with the exceptions of the Null Command and the Keyscan Data Output Command. An all zeros (00h) byte indicates the presence of new keyscan information while all ones (FFh) indicate no new keyscan information. For the Null and Keyscan Data Output commands, the first byte output is still the status byte followed by five bytes containing the data from the five keyscan rows as described above and in the Output Data Bytes section. The status byte is reset upon completion of a Keyscan Data Output command in the same fashion as KBINT. The MSC7170 can also be commanded into a low power or "standby" mode (see Mode Set command). In this mode all operation, including the internal oscillator, of the MSC7170 ceases. The only exception is the key scan detection circuitry which, on any key pad activity (depress or release), will cause the MSC7170 to return to normal operation. The MSC7170 will be fully operational within 10 msec (max) after return to normal operation. The wake-up cycle includes a full scan of the key matrix. KBINT will be pulled low to indicate full wake-up. Normal operation is also resumed when the ENABLE line is taken low. In this case, a scan of the key matrix is not executed, nor is the KBINT line pulled low to indicate full wake-up. The RESET and ENABLE lines shall be maintained at logic high levels during standby operation. All segment outputs go to a high impedance state while in standby mode. The SPI interface lines (SLCK, SIMO, and SOMI) will not interfere with the operation of the SPI network when the standby mode is properly selected. To ensure correct operation of the SPI network, the standby mode of the MSC7170 should always be selected before the logic supply is switched off. The following sequence of events should be followed to enter standby mode: 1) 2) 3) Set duty cycle to zero percent Turn off high voltage (VDISP) Send low power (standby) "on" command
Following wake-up, the high voltage should be turned on prior to setting a duty cycle greater than zero percent. The MSC7170 may be commanded into Blank and Lamp Test modes. For Blank mode, the DUTY and SEGn-1 to SEGn-35 outputs remain at a continuous low level while the SEGn36 outputs assume a high level. The outputs remain at this level until the command is deselected. For Lamp Test mode, the DUTY output assumes a maximum duty cycle condition and the SEGn outputs are all forced to the on condition regardless of input data. The MSC7170 accepts a reset signal from the microprocessor or other controller. There shall be no internal pull-up resistor on this signal. The state of the MSC7170 following a reset is as follows: a) b) c) d) e) f) All segment driver outputs are low The number of display digits is 16 2. The display duty cycle is set to 0 Display Data Buffers are not cleared SPI registers are reset Keyscan registers are reset
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MSC7170-XX
The MSC7170 is protected against thermal overload or other failure caused by extreme display configurations (e.g. Lamp Test) or due to output short circuits to high voltage supply, ground, or another output. These shall be no performance degradation once the short circuit is removed.
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Semiconductor Commands Description
No. 0 1 2 3 4 Instruction Address Setup Character Code Setup Display Duty Cycle Setup Display Digits Setup Mode Setup Byte 1 2 1 2 1 2 1 1 1 2 5 Cursor Setup 3 4 5 6 7 Keyscan Data Output Null 1 1 c7 1 X 1 b7 1 DC7 1 1 1 C1-7 C2-7 1 0 c6 0 X 0 b6 0 DC6 0 1 1 C1-6 C2-6 1 0 c5 0 X 0 b5 1 DC5 1 0 0 C1-5 C2-5 1 0 c4 0 a4 1 b4 0 DC4 1 0 1 C1-4 C2-4 0 0 c3 X a3 X b3 X DC3 n3 X X C1-3 C2-3 X 0 c2 X a2 X b2 X DC2 n2 m2 X C1-2 C2-2 X 0
MSC7170-XX
c1 X a1 X b1 DC9 DC1 n1 m1 X C1-1 C1-9 C2-1 C2-9 X 0
c0 X a0 X b0 DC8 DC0 n0 m0 X C1-0 C1-8 C2-0 C2-8 X 0
C1-15 C1-14 C1-13 C1-12 C1-11 C1-10 C2-15 C2-14 C2-13 C2-12 C2-11 C2-10
Address Setup Command This command is used to setup a start position of display character code writing and must be executed before the desired character code is sent. In applications using less than the full 16-digit pair capability, only the first 2n memory locations are used. For example, if n = 12-digit pair is selected, only addresses 0 through 23 are used. Row 1 display data (SEG1 outputs) is stored in addresses 0 through 11 while Row 2 display data (SEG2 outputs) is stored in addresses 12 through 23. All bytes following Bytes 1 and 2 are treated as character code data bytes. Address 0 is set after reset.
c7 Byte 1 1 d7 Byte 2 X
c6 0 d6 X
c5 0 d5 X
c4 0 d4 a4
c3 X d3 a3
c2 X d2 a2
c1 X d1 a1
c0 X d0 a0
a4 to a0 : 00000=00h=0 : 11111=1Fh=31
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Semiconductor
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Character Code Setup Command This command is used to specify the character to be displayed in the display location previously specified by the Address Setup command. A built-in automatic address increment function simplifies writing more than one display character code. All bytes transmitted after Byte 2 are treated as character code data for successive locations. The internal address counter will be automatically incremented from the address set using the Address Set command through address 31 (or character 32), while executing valid write cycles, regardless of the number of digit pairs as defined using the Number of Display Digits Setup command. In the event that additional data is input to the MSC7170 following a valid write to address 31, the address counter will wraparound and continue to increment (to address 0 etc.) with write cycles disabled. This prevents overwriting of the memory.
c7 Byte 1 1 d7 Byte 2 b7 c6 0 d6 b6 c5 0 d5 b5 c4 1 d4 b4 c3 X d3 b3 c2 X d2 b2 c1 X d1 b1 c0 X d0 b0
b4 to b0 : 8-bit character code -- Select one of 256 codes
Display Duty Cycle Setup Command This command is used to set the duty cycle of the display. The time allocated to a 1-digit display is 1024T, where T is the period of the internal oscillator (fOSC). The display time for each digit may be specified as 0 to 976T in increment of T. Entries greater than 976 default to 976. The display duty cycle is calculated by dividing the input duty cycle value, DC, by 1024 times the number of digits, n, commanded to display. Note that the percent duty cycle depends on how many digits (characters) are displayed.
c7 Byte 1 1 d7 Byte 2 DC7 c6 0 d6 DC6 c5 1 d5 DC5 c4 0 d4 DC4 c3 X d3 DC3 c2 X d2 DC2 c1 DC9 d1 DC1 c0 DC8 d0 DC0
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Semiconductor Number of Display Digits Setup Command
MSC7170-XX
This command is used to set the number of digits to be displayed. The number of digits selectable ranges from 1 to 16.
c7 Byte 1 1 c6 0 c5 1 c4 1 c3 n3 c2 n2 c1 n1 c0 n0
n3 to n0 : 0000=0h=16-digit pair : 0001=1h=1-digit pair : : 1111=Fh=15-digit pair
Mode Setup Command This command is used to select an operation mode for the MSC7170. Lamp Test and Blank modes turns all 36 segments of each displayable digit (as set by the Number of Display Digits Setup command) to the ON and OFF states respectively. The contents of the display buffer are not affected by either of these modes. The normal operation mode returns after reset. Low Power mode is described earlier.
c7 Byte 1 1 m2 0 0 0 0 1 1 1 1 c6 1 m1 0 0 1 1 0 0 1 1 c5 0 m0 0 1 0 1 0 1 0 1 c4 0 Mode Normal operation Lamp test (All display ON) Low power Normal operation Blank (All display OFF) Normal operation Normal operation Normal operation c3 X c2 m2 c1 m1 c0 m0
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Semiconductor Cursor Setup Command
MSC7170-XX
This command is used to specify the on/off state of cursor segments (SEGn-36) in the display. The cursor outputs are issued inversely to allow an external PNP transistor to be used in applications requiring high current drive capability. Therefore, a logic high, l, in a given bit position will turn on the associated cursor. In applications requiring low current (less than 15 mA) drive capability, the cursor outputs may drive the VF display tube directly. In these applications, setting to "0" turns on the cursor.
c7 Byte 1 1 d7 Byte 2 Byte 3 Byte 4 Byte 5 C1-7 C2-7 c6 1 d6 C1-6 C2-6 c5 0 d5 C1-5 C2-5 c4 1 d4 C1-4 C2-4 c3 X d3 C1-3 C2-3 c2 X d2 C1-2 C2-2 c1 X d1 C1-1 C1-9 C2-1 C2-9 c0 X d0 C1-0 C1-8 C2-0 C2-8
C1-15 C1-14 C1-13 C1-12 C1-11 C1-10 C2-15 C2-14 C2-13 C2-12 C2-11 C2-10
Keyscan Data Output Command This command is used to read keyscan data via the SPI interface and has no effect on the operation or state of the display portion of the MSC7170. Upon completion of this command the KBINT output is reset to its non-active state and the keyscan function is stopped. All bytes after Byte 1 are ignored.
c7 Byte 1 1 c6 1 c5 1 c4 0 c3 X c2 X c1 X c0 X
NULL Command This command has the same function as the Keyscan Data Output command with the exception that KBINT is not reset and the keyscan function continues to scan the key matrix. The keyscan may stop momentarily to prevent changing data while data output is in progress. All bytes after Byte 1 are ignored.
c7 Byte 1 0 c6 0 c5 0 c4 0 c3 0 c2 0 c1 0 c0 0
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Semiconductor Output Data Byte Description * Status output
MSC7170-XX
The following byte is output from the MSC7170 during execution of every SPI command with the exceptions of the Keyscan Data Output and Null commands. The status byte is issued for each byte of the input command sequence.
d7 Byte 1 s7
d6 s6
d5 s5
d4 s4
d3 s3
d2 s2
d1 s1
d0 s0 Status
s7 to s0: indicates change status from last SPI transaction 00h = change, FFh = no change
* Keyscan data output The following bytes are output from the MSC7170 during execution of the Keyscan Data Output and Null commands. The output of keyscan data wraps around to byte 1 for transactions of more than six bytes.
d7 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 sij X X X X X d6 X X X X X d5 s16 s26 s36 s46 s56 d4 s15 s25 s35 s45 s55 d3 s14 s24 s34 s44 s54 d2 s13 s23 s33 s43 s53 d1 s12 s22 s32 s42 s52 d0 s11 s21 s31 s41 s51 Row 1 Row 2 Row 3 Row 4 Row 5
: i=ROW1 to 5, j =Col1 to 6 sij=1: Switch on sij=0: Switch off
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Semiconductor Character Codes and Character Patterns (for ROM Code 01: Standard)
MSB: D7 - D4 0
LSB: D3 - D0
MSC7170-XX
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Note:
These character patterns are user programmable and can be selected by mask option. 23/26
Semiconductor Correspondence between Segment Outputs and VF Display Tube Dots
MSC7170-XX
VF Dot: IC Pin:
1-1 SEGn-1
2-1 SEGn-2
3-1 SEGn-3
4-1 SEGn-4
5-1 SEGn-5
VF Dot: IC Pin:
1-2 SEGn-6
2-2 SEGn-7
3-2 SEGn-8
4-2 SEGn-9
5-2 SEGn-10
VF Dot: IC Pin:
1-3 SEGn-11
2-3 SEGn-12
3-3 SEGn-13
4-3 SEGn-14
5-3 SEGn-15
VF Dot: IC Pin:
1-4 SEGn-16
2-4 SEGn-17
3-4 SEGn-18
4-4 SEGn-19
5-4 SEGn-20
VF Dot: IC Pin:
1-5 SEGn-21
2-5 SEGn-22
3-5 SEGn-23
4-5 SEGn-24
5-5 SEGn-25
VF Dot: IC Pin:
1-6 SEGn-26
2-6 SEGn-27
3-6 SEGn-28
4-6 SEGn-29
5-6 SEGn-30
VF Dot: IC Pin:
1-7 SEGn-31
2-7 SEGn-32
3-7 SEGn-33
4-7 SEGn-34
5-7 SEGn-35
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Semiconductor
MSC7170-XX
APPLICATION CIRCUIT
KEYBOARD MATRIX S11 S12 S13 S14 S15 S16 S21 S22 S23 S24 S25 S26 S31 S32 S33 S34 S35 S36 S41 S42 S43 S44 S45 S46 S51 S52 S53 S54 S55 S56 P VDISP
DISPLAY VOLTAGE AND AC FILAMENT SUPPLY VGRID FIL1 FIL2
12345 ROW 5V
From microprocessor
1
2
3 COL
4
5
6
VDD SIMO SOMI SCLK ENABLE RESET KBINT OSCl OSCO
VDISP SYNC SEG1-36
NC
MSC7170
SEG2-36
1
2
FILAMENT SEG1-1 to SEG1-35 SEG2-1 to SEG2-35 STANDBY DATA CLOCK DUTY VSS1 P STANDBY DATA CLOCK DUTY GRID1-12 35 35
DOT MATRIX VF DISPLAY TUBE
VSS2 RESONATOR S
12
MSC7171
VDD VSS VDISP
S
P
P
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Semiconductor
MSC7170-XX
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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